NBTI is becoming one of the dominant circuit reliability concerns in nano-scale technologies. We believe that designers can combat NBTI degradation using appropriate circuit constraints. This paper presents a design technique to tolerate NBTI degradation by gate sizing. We provide an NBTI-aware gate sizing problem formulation and propose a solution method. The experimental results for MCNC?91 benchmark circuits show that for NBTI tolerance the purposed method results in less than 1% area increase in most cases while a formulation based on traditional performance focused methods may lead to over 4% area increase.