To address the reliability concerns that affect the lifetime of complex systems-on-a-chip (SoC) designs, a concurrent on-line SoC test scheme is essential to circumvent the prohibitive costs -- test time and test power - associated with off-line SoC test. A Test Infrastructure IP (TI-IP) is deployed within the network-on- chip (NoC) based SoC design to provide on-line test support while managing the intrusion of test into the executing applications within the system. This research describes the architecture and operation of a TI-IP capable of testing SoCs and demonstrates its operation in two SoC test configurations developed using research domain application and test benchmarks.