8th International Symposium on Quality Electronic Design (ISQED'07)
An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization
San Jose, California
March 26-March 28
ISBN: 0-7695-2795-7
DOI Bookmark:
http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.34
In this paper we report a set of statistical static timing (SSTA) studies performed on a UMC test chip manufactured at 90nm process node. We employed comprehensive variation extraction techniques to prepare a complete set of input variation data for the technology node. Our studies include SSTA runs in the presence of various process variation components, comparison of SSTA results to those obtained from traditional corner flows, and statistical optimization to improve parametric yield of the design. We observed that generally traditional corner methodologies produce more pessimistic results than those obtained from the SSTA. We also noticed that it is hard to guarantee pessimism in the traditional analyses, unless all the process corner combinations are sampled.
Citation:
Ayhan Mutlu, Kelvin J. Le, Mustafa Celik, Dar-sun Tsien, Garry Shyu, Long-Ching Yeh, "An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization," isqed, pp.677-684, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007
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