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8th International Symposium on Quality Electronic Design (ISQED'07)
An Automated and Fast OPC Algorithm for OPC-Aware Layout Design
San Jose, California
March 26-March 28
ISBN: 0-7695-2795-7
ASCII Text
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Ye Chen, Zheng Shi, Xiaolang Yan, "An Automated and Fast OPC Algorithm for OPC-Aware Layout Design," Quality Electronic Design, International Symposium on, pp. 782-787, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007.
 
 
BibTex
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@article{ 10.1109/ISQED.2007.32,
author = {Ye Chen and Zheng Shi and Xiaolang Yan},
title = {An Automated and Fast OPC Algorithm for OPC-Aware Layout Design},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2007},
isbn = {0-7695-2795-7},
pages = {782-787},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.32},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - An Automated and Fast OPC Algorithm for OPC-Aware Layout Design
SN - 0-7695-2795-7
SP782
EP787
A1 - Ye Chen,
A1 - Zheng Shi,
A1 - Xiaolang Yan,
PY - 2007
KW - null
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Ye Chen, Zhejiang University, China
Zheng Shi, Zhejiang University, China
Xiaolang Yan, Zhejiang University, China
To reduce design spin time, OPC-unfriendly spots in IC layout should be found out by designer before tape-out. This can be done by firstly running a "trial OPC" step on the layout, followed by running an ORC step to verify the result. In this paper we introduce a new OPC algorithm using an edge bias modeling method. When given a piece of sample post-OPC layout, software based on this algorithm can automatically correct a design with similar recipe but dozens of times faster than traditional model-based method, at cost of some accuracy loss. This makes the algorithm a good choice for "trial OPC".
Citation:
Ye Chen, Zheng Shi, Xiaolang Yan, "An Automated and Fast OPC Algorithm for OPC-Aware Layout Design," isqed, pp.782-787, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007
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