An important factor which greatly affects the power consumption and the delay of a circuit is the input capacitance of its gates. High input capacitances increase the power consumption as well as the time for charging and discharging the inputs. Current approaches address this problem either through gate-level only resynthesis and optimization, or indirectly through transistor-level synthesis aimed for transistor count reduction. In this paper a method is presented to synthesize complex gates at the transistor level with explicit consideration of the switching activity profile for the gate. The method finds a power efficient implementation by giving priority to transistor inputs with higher switching activity, while keeping the overall number of required transistors low. Experimental results demonstrate the benefit of the approach.