A thermal-aware placement is proposed for FPGAs to reduce the peak temperature and maximum on-chip gradient temperature. A new thermal cost is defined for the simulation annealing core of the placer based on the electrostatic charge model instead of extracting temperature profile in each simulation iteration. The thermal cost change rather than its actual value is derived to keep the runtime complexity of the cost evaluation algorithm linear with the number of used logic blocks. Results show an average of 73% and 51% reductions in the standard deviation and maximum gradient of temperature with less than 4% average wiring and delay penalty.