8th International Symposium on Quality Electronic Design (ISQED'07)
System Level Estimation of Interconnect Length in the Presence of IP Blocks
San Jose, California
March 26-March 28
ISBN: 0-7695-2795-7
With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-scale circuits. Up to now, the proposed techniques for wirelength estimation in the presence of IP blocks approached this problem either in a flat framework based on the geometrical structure of the circuit or in a hierarchical framework based on uniform distribution property for standard cells. In this paper, we propose a technique for hierarchical derivation of wirelength estimation in the presence of single and multiple blockages using Rent?s parameter of the circuit by assuming non-uniform probability distribution for standard cells. To measure the accuracy of our estimation, we compared our results with the results of placement and routing using a commercial CAD tool. The results illustrate that in the presence of multiple IP blocks, the average error of our technique is less than 8%, as compared to its counterparts with the average error of 35% and 150%.
Index Terms:
Wirelength Estimation, Rent's Rule, Hierarchical Placement, Large-scale Circuits, IP Blocks, Non-Uniform Probability Distribution
Citation:
Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh, "System Level Estimation of Interconnect Length in the Presence of IP Blocks," isqed, pp.438-443, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007
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