A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations

I
ISQED
2007
8th International Symposium on Quality Electronic Design (ISQED'07)
Abstract - A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Manoj Kumar Goparaju Articles by Spyros Tragoudas

8th International Symposium on Quality Electronic Design (ISQED'07)

San Jose, California

March 26-March 28

ISBN: 0-7695-2795-7

	ASCII Text	x
	Manoj Kumar Goparaju, Spyros Tragoudas, "A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations," Quality Electronic Design, International Symposium on, pp. 420-425, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007.

	BibTex	x
	@article{ 10.1109/ISQED.2007.12, author = {Manoj Kumar Goparaju and Spyros Tragoudas}, title = {A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2795-7}, pages = {420-425}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.12}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations SN - 0-7695-2795-7 SP420 EP425 A1 - Manoj Kumar Goparaju, A1 - Spyros Tragoudas, PY - 2007 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Manoj Kumar Goparaju, Southern Illinois University Carbondale, USA

Spyros Tragoudas, Southern Illinois University Carbondale, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.12

Threshold Logic Gates (TLG) are prone to manufacturing defects that impact weight values which inadvertently affect the functionality of the gate. A method is presented for the design of threshold logic gates to tolerate manufacturing defects to the maximum possible extend. A novel solution is presented for the problem of identifying a fault tolerant k-input TLG for any value of k.

Citation:

Manoj Kumar Goparaju, Spyros Tragoudas, "A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations," isqed, pp.420-425, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.