Minimizing FPGA Reconfiguration Data at Logic Level

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7th International Symposium on Quality Electronic Design (ISQED'06)

San Jose, California

March 27-March 29

ISBN: 0-7695-2523-7

	ASCII Text	x
	Krishna Raghuraman, Haibo Wang, Spyros Tragoudas, "Minimizing FPGA Reconfiguration Data at Logic Level," Quality Electronic Design, International Symposium on, pp. 219-224, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006.

	BibTex	x
	@article{ 10.1109/ISQED.2006.87, author = {Krishna Raghuraman and Haibo Wang and Spyros Tragoudas}, title = {Minimizing FPGA Reconfiguration Data at Logic Level}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2523-7}, pages = {219-224}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.87}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Minimizing FPGA Reconfiguration Data at Logic Level SN - 0-7695-2523-7 SP219 EP224 A1 - Krishna Raghuraman, A1 - Haibo Wang, A1 - Spyros Tragoudas, PY - 2006 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Krishna Raghuraman, Southern Illinois University, Carbondale, IL

Haibo Wang, Southern Illinois University, Carbondale, IL

Spyros Tragoudas, Southern Illinois University, Carbondale, IL

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.87

A framework that relates the size of FPGA reconfiguration data to the number of minterms of a specially constructed function is presented. Three techniques, variable mapping optimization, circuit don?t-care modification, and look-up table input permutation, are developed to minimize minterms of the special function. The method to integrate the proposed techniques into FPGA design automation flow is discussed and experimental results are presented.

Citation:

Krishna Raghuraman, Haibo Wang, Spyros Tragoudas, "Minimizing FPGA Reconfiguration Data at Logic Level," isqed, pp.219-224, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006

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