Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two circuit-level techniques to efficiently yet economically improve SEU tolerance of static CMOS digital circuits. We also developed a "RObustness COmpiler (ROCO)" to integrate these techniques into the existing design flow to achieve high level of reliability at low design cost. Experiment results show that the proposed methodology is able to greatly improve the circuits? SEU tolerance with zero timing overhead and very limited area penalty.