In this paper, we propose a via distribution model for yield estimation. The proposed model expresses a relationship between the number of vias and wire length. We can also estimate the total number of vias in a circuit, which is derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from a gate-level netlist and layout area. We extract model parameters from the commercial chips designed for 0.18-?m and 0.13-?m CMOS processes, and demonstrate yield degradation caused by vias.