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7th International Symposium on Quality Electronic Design (ISQED'06)
Variational Interconnect Delay Metrics for Statistical Timing Analysis
San Jose, California
March 27-March 29
ISBN: 0-7695-2523-7
Praveen Ghanta, Arizona State University, Tempe.
Sarma Vrudhula, CSE, Arizona State University, Tempe.
For statistical timing analysis and physical design optimization, interconnect delay metrics that model the delay as a function of the metal process variations are very important. Accurate linear or at most second order delay models in terms of the process variables are necessary to efficiently propagate uncertainty in the state-of-the-art VLSI designs with millions of transistors and on chip interconnects. In this paper1, we develop a method to extend the traditional moment based delay analysis of interconnects to consider the impact of Gaussian metal process variations and obtain mean-square optimal linear delay models for interconnects. We consider linear models for the variations in the conductance and capacitance of interconnects and represent the moments (m_0, m_1, m_2) of the interconnect impulse response as a first order orthogonal polynomial series expansion in the process variables^2. We obtain the coefficients of the expansion by using the Galerkin residual error minimization method on the recursive equations that relate the interconnect moments (m_0, m_1, m_2). We compare the accuracy of our approach against SPICE based Monte Carlo simulations and demonstrate a good match.
Citation:
Praveen Ghanta, Sarma Vrudhula, "Variational Interconnect Delay Metrics for Statistical Timing Analysis," isqed, pp.19-24, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006
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