Statistical Static Timing Analysis (SSTA) tools have mostly addressed the process variations of devices and lumped interconnect RC effects. This paper provides an overview of interconnect process variations of capacitive coupling and its effect on crosstalk delay and noise. The correlations among parallel plate, lateral and total capacitance is shown. Correlations between resistance and capacitance are illustrated to enable development of a simple and efficient model for delay and noise analysis. Experimental results are shown to validate the assumptions on the linearity of sensitivity of delay and noise to process variations. A methodology to account for process variations in crosstalk delay and noise is proposed.