A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology

I
ISQED
2006
7th International Symposium on Quality Electronic Design (ISQED'06)
Abstract - A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology

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7th International Symposium on Quality Electronic Design (ISQED'06)

San Jose, California

March 27-March 29

ISBN: 0-7695-2523-7

	ASCII Text	x
	Ali Bastani, Charles A. Zukowski, "A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology," Quality Electronic Design, International Symposium on, pp. 312-317, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006.

	BibTex	x
	@article{ 10.1109/ISQED.2006.12, author = {Ali Bastani and Charles A. Zukowski}, title = {A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2523-7}, pages = {312-317}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.12}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology SN - 0-7695-2523-7 SP312 EP317 A1 - Ali Bastani, A1 - Charles A. Zukowski, PY - 2006 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Ali Bastani, Columbia University

Charles A. Zukowski, Columbia University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.12

In this paper, we investigate the use of monotonic static CMOS logic within a high performance carry lookahead adder (CLA) in the context of a 65nm technology with significant leakage. The goal is a good compromise between speed, power, and noise immunity. We compare the monotonic static CMOS 64b CLA with domino and static CMOS adders with respect to speed and power consumption, using a predictive dual gate oxide 65nm technology with significant gate leakage. The comparison shows that monotonic-static CMOS is a potentially useful alternative in such applications. Compared to domino and static CMOS, it can provide advantages in evaluation speed and static power for a set of nominal gates sizes.

Citation:

Ali Bastani, Charles A. Zukowski, "A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology," isqed, pp.312-317, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006

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