The recent migration to DSM process geometries and very large gate counts, has created a need for low power design and multi-voltage designs as standard rather than the exception. The variety of power optimization and power planning tools has resulted in ad-hock modification to existing design flows to accommodate the new requirements. This has given rise to wide variation in the QOR of the silicon that incorporates these design features. The panel will review and discuss places in the design flow where power planning and optimization are beneficial to improving QOR and also some of the analysis and signoff limitations to the automation that is available and directed at this task.