Design for Manufacturability (DfM) is a design verification methodology linked to a set of requirements that can be perceived as gray area within the design rule check (DRC) approach based on rigid pass/fail criteria. This is because the DfM rules, unlike DRC, are not directly responsible for the functionality of individual devices, but are broadly scoped to address the die yield over the process corners. At the same time, all design rules are to ensure high performance and profit margins. Therefore, the distinction between DfM and DRC rules is often artificial and confusing. In this paper, we propose how to combine all design rules into one enforceable deck, regardless of their origin, and introduce an implementation cutoff lines decided by technology and business factors. This new methodology is based on the Failure Mode and Effect Analysis (FMEA) and Return on Investment (RoI). FMEA, involving the criticality, occurrence, and detectability of failure modes, is demonstrated for DfM rules focused on System on Chip (SoC). The results are then correlated to those of the RoI approach for the same set of rules.