As higher operating frequencies are achieved in advanced digital designs, the influence of inductance on interconnect delays can no longer be ignored. A solution is proposed to prevent parasitic inductance effects on signal integrity by pre-estimating their impact during the early phases of the design flow. A pre-layout inductance modeling approach for on-chip advanced digital design interconnects, based on a relevant description of the current return path, is suggested. Representative structures for corner models are presented and assessed. They give minimal and maximal inductance value estimation. Finally, an original ring oscillator test structure is developed and implemented to highlight inductance impact on interconnect delay for a realistic digital environment. Silicon measurements match expected results and validate the presented corner models and methodology.