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7th International Symposium on Quality Electronic Design (ISQED'06)
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level
San Jose, California
March 27-March 29
ISBN: 0-7695-2523-7
ASCII Text
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Arkan Abdulrahman, Spyros Tragoudas, "Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level," Quality Electronic Design, International Symposium on, pp. 300-305, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006.
 
 
BibTex
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@article{ 10.1109/ISQED.2006.104,
author = {Arkan Abdulrahman and Spyros Tragoudas},
title = {Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2006},
isbn = {0-7695-2523-7},
pages = {300-305},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.104},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level
SN - 0-7695-2523-7
SP300
EP305
A1 - Arkan Abdulrahman,
A1 - Spyros Tragoudas,
PY - 2006
KW - null
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Arkan Abdulrahman, Southern Illinois University, Carbondale
Spyros Tragoudas, Southern Illinois University, Carbondale
A functional Automatic Test Pattern Generation (ATPG) for embedded core testing is presented that meets power constraints requirements and time to market consideration. Quick turnaround time for the ATPG is obtained by utilizing compact sets of test vectors. Use of test functions for the embedded cores control the switching activity so that the generated test vectors meet constraints on power dissipation. Concurrency is guaranteed with the use of test functions (as opposed to patterns) and appropriate I/O pin TAM allocation during a compact ATPG process that benefits from pre-existing test vectors. Low power dissipation is also facilitated by test functions and is driven by a metric that requires that a very small portion of each core net-list is available.
Citation:
Arkan Abdulrahman, Spyros Tragoudas, "Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level," isqed, pp.300-305, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006
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