Sixth International Symposium on Quality of Electronic Design (ISQED'05) Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis San Jose, California March 21-March 23 ISBN: 0-7695-2301-3
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.97
As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for high-level synthesis. By evaluating power supply noise in the early design stage, the proposed method generates schedule and resource allocation with a floorplan such that the power supply noise is minimized. To achieve the goal, we formulated the problem using a genetic algorithm. Compared to designs that do not consider supply noise, the proposed methodology reduces power supply noise up to 44%.
Citation:
Dongku Kang, Yiran Chen, Kaushik Roy, "Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis," isqed, pp.48-53, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||