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Sixth International Symposium on Quality of Electronic Design (ISQED'05)
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization
San Jose, California
March 21-March 23
ISBN: 0-7695-2301-3
Rahul Rao, University of Michigan, Ann Arbor, MI
Kanak Agarwal, University of Michigan, Ann Arbor, MI
Anirudh Devgan, Austin Research Laboratories, IBM, Austin, TX
Kevin Nowka, Austin Research Laboratories, IBM, Austin, TX
Dennis Sylvester, University of Michigan, Ann Arbor, MI
Richard Brown, University of Utah, Salt Lake City, UT
Parametric yield loss has become a serious concern in leakage dominated technologies. In this paper, we discuss the impact of leakage on parametric yield and show that leakage can cause yield window to shrink by imposing a two-sided constraint on the window. We present a mathematical framework for yield estimation under device process variation for a given power and frequency constraints. The model is validated against Monte Carlo simulations for an industry process and is shown to have typical error of less than 5%. We then demonstrate the importance of optimal supply voltage selection for yield maximization. We also investigate the sensitivity of parametric yield to applied frequency and power constraints. Finally, we apply the proposed framework to the problem of maximizing the shipping frequency in the presence of given yield and power constraints.
Citation:
Rahul Rao, Kanak Agarwal, Anirudh Devgan, Kevin Nowka, Dennis Sylvester, Richard Brown, "Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization," isqed, pp.284-290, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005
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