Sixth International Symposium on Quality of Electronic Design (ISQED'05) Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits San Jose, California March 21-March 23 ISBN: 0-7695-2301-3
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.77
Double Gate (DG) FETs have emerged as the most promising technology for sub-50nm transistor design. However, analysis and control of the gate tunneling leakage in DGFET is necessary to fully exploit their advantages. In this paper we have modeled (numerically and analytically) and analyzed gate-to-channel leakage in different DGFET structures, namely, doped body symmetric device (SymDG) with polysilicon gates, intrinsic body symmetric device with metal gates (MGDG) and intrinsic body asymmetric device (AsymDG) with different front and back gate materials. It is observed that, use of (near-mid-gap) metal gate and intrinsic body can result in 3-4X reduction in gate-to-channel leakage compared to the SymDG structure.
Citation:
Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy, "Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits," isqed, pp.410-415, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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