As nanometer technology has increased functionality of integrated circuits, so has it also presented challenges to acceptable yield levels. With defects per million (DPM) rates increasing, designers and manufacturers are looking for ways to enhance yield outcome. Improvements can be made by screening for defects more efficiently or by eliminating the issues leading to defects, which is the basis for any design for manufacturing (DFM) methodology. Standard test practices have become less effective for nanometer designs. However, advanced test methods show improvements can be made in three areas: increased defect coverage, increased yield learning and decreased cost.