Low Voltage Test in Place of Fast Clock in DDSI Delay Test

I
ISQED
2005
Sixth International Symposium on Quality of Electronic Design (ISQED'05)
Abstract - Low Voltage Test in Place of Fast Clock in DDSI Delay Test

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Sixth International Symposium on Quality of Electronic Design (ISQED'05)

San Jose, California

March 21-March 23

ISBN: 0-7695-2301-3

	ASCII Text	x
	Haihua Yan, Gefu Xu, Adit D. Singh, "Low Voltage Test in Place of Fast Clock in DDSI Delay Test," Quality Electronic Design, International Symposium on, pp. 316-320, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005.

	BibTex	x
	@article{ 10.1109/ISQED.2005.75, author = {Haihua Yan and Gefu Xu and Adit D. Singh}, title = {Low Voltage Test in Place of Fast Clock in DDSI Delay Test}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2301-3}, pages = {316-320}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.75}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Low Voltage Test in Place of Fast Clock in DDSI Delay Test SN - 0-7695-2301-3 SP316 EP320 A1 - Haihua Yan, A1 - Gefu Xu, A1 - Adit D. Singh, PY - 2005 KW - delay test KW - low voltage test KW - defect KW - ATE VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Haihua Yan, Auburn University

Gefu Xu, Auburn University

Adit D. Singh, Auburn University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.75

By testing the CUT at lower supply voltages, the CUT will slow down and thus slow low-cost testers can be used to perform DDSI test. Apart from this, because the delay fault size is known in DDSI test, this information can be further used to diagnose the causing mechanism behind the delay faults. Experimental results were presented to investigate the potential of the method.

Index Terms:

delay test, low voltage test, defect, ATE

Citation:

Haihua Yan, Gefu Xu, Adit D. Singh, "Low Voltage Test in Place of Fast Clock in DDSI Delay Test," isqed, pp.316-320, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005

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