Interconnect-related effects have become significant factors that can affect complex nanometer designs, such as memories. Thus, a robust memory design methodology needs to include the accurate modeling of interconnect parasitics and interconnect process variations.In this paper we present a statistical design approach to study the impact of interconnect process variations on memory performance and design. This approach uses 3D parasitic extraction, circuit simulation, Monte Carlo and sensitivity analysis to determine the parasitic and performance sensitivities to interconnect process parameter variations for a 90nm memory design example.The sensitivity analysis results can be used to optimize the memory circuit design and layout to further improve memory performance and robustness.