High-density and high-performance single-port and dual-port SRAM increasingly occupy the majority of the chip area in deep submicron (DSM) System-on-Chip (SoC) designs. These designs also require a larger number of individual SRAM instances to serve the increasing number of functions in SoCs. Hence, a complex SoC design may consist of 10Mb or more of embedded SRAM and use up to a few hundred individual memory instances with various sizes and configurations. We have previously reported on the need for high-density and high-performance SRAM with good yieldability and manufacturability and our results on the industry's smallest and fastest embedded 6T-SRAM bitcells in 180nm and 130nm generation standard CMOS processes. We have described how these SRAM bitcells are robust by design even while aggressively driving density and performance.In this paper we extend the discussion on embedded SRAM bitcell robustness and ease of manufacturing to include memory and chip-level considerations, such as memory performance and routing congestion. We present our results on the advantages of using metal 2 bitline bitcells in terms of memory performance and we highlight the advantages of providing unrestricted or only partially restricted routing over memory capability to chip-level routing metallization for minimizing chip-level routing congestions and hence, improve overall chip area utilization, i.e. chip-level effective density.