Early Assessment of Leakage Power for System Level Design

I
ISQED
2005
Sixth International Symposium on Quality of Electronic Design (ISQED'05)
Abstract - Early Assessment of Leakage Power for System Level Design

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	Similar Articles Articles by C. Talarico Articles by B. Pillilli Articles by K. L. Vakati Articles by J. M. Wang

Sixth International Symposium on Quality of Electronic Design (ISQED'05)

San Jose, California

March 21-March 23

ISBN: 0-7695-2301-3

	ASCII Text	x
	C. Talarico, B. Pillilli, K. L. Vakati, J. M. Wang, "Early Assessment of Leakage Power for System Level Design," Quality Electronic Design, International Symposium on, pp. 133-136, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005.

	BibTex	x
	@article{ 10.1109/ISQED.2005.50, author = {C. Talarico and B. Pillilli and K. L. Vakati and J. M. Wang}, title = {Early Assessment of Leakage Power for System Level Design}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2301-3}, pages = {133-136}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.50}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Early Assessment of Leakage Power for System Level Design SN - 0-7695-2301-3 SP133 EP136 A1 - C. Talarico, A1 - B. Pillilli, A1 - K. L. Vakati, A1 - J. M. Wang, PY - 2005 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

C. Talarico, University of Arizona, Tucson, AZ

B. Pillilli, University of Arizona, Tucson, AZ

K. L. Vakati, University of Arizona, Tucson, AZ

J. M. Wang, University of Arizona, Tucson, AZ

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.50

This paper presents a system level methodology for analyzing leakage power in the early stages of a system design. The assessment of leakage takes into accounts the simultaneous effect of threshold-voltage (Vt), oxide thickness (tox), device width (W), the inputs applied and statistical process variations. The approach has been validated by applying it to the design of a digital signal processing system. The results indicate that our power estimation technique is within 10% of SPICE, with the benefit of executing 15X faster.

Citation:

C. Talarico, B. Pillilli, K. L. Vakati, J. M. Wang, "Early Assessment of Leakage Power for System Level Design," isqed, pp.133-136, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005

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