The increase in the pattern complexity due to the optical proximity correction (OPC), the tight requirements for critical dimension (CD) control and the difficulties in defect inspections make the cost of the IC manufacturing more expensive. To alleviate the high cost, manufacturing requirements must be handled up front at the design stage to improve the quality and yield of IC. In this paper, we demonstrate the extraction of critical area to detect failures and the new lithography simulation method for the full-chip level OPCed layout. The methodology has been used in our mask verification process that is called litho-friendly layout (LFL). For the critical area extraction, we present three approaches using process window, normalized image log-slope (NILS) and edge placement error (EPE). For full-chip level simulation, we introduce the automatic calibration method for simulation process parameters, the mask decomposition method and the selective simulation method. The verification process includes lithography process simulation, print-image based LVS (layout vs. schematic) and DRC (design rule check). We also demonstrate that the LFL can provide guidelines for better OPC of sub-80nm processes.