Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms

I
ISQED
2005
Sixth International Symposium on Quality of Electronic Design (ISQED'05)
Abstract - Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms

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	Similar Articles Articles by Ananth Somayaji Goda Articles by Gautam Kapila

Sixth International Symposium on Quality of Electronic Design (ISQED'05)

San Jose, California

March 21-March 23

ISBN: 0-7695-2301-3

	ASCII Text	x
	Ananth Somayaji Goda, Gautam Kapila, "Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms," Quality Electronic Design, International Symposium on, pp. 416-420, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005.

	BibTex	x
	@article{ 10.1109/ISQED.2005.41, author = {Ananth Somayaji Goda and Gautam Kapila}, title = {Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2301-3}, pages = {416-420}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.41}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms SN - 0-7695-2301-3 SP416 EP420 A1 - Ananth Somayaji Goda, A1 - Gautam Kapila, PY - 2005 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Ananth Somayaji Goda, Texas Instruments India Pvt Ltd, Bangalore, India

Gautam Kapila, Texas Instruments India Pvt Ltd, Bangalore, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.41

We present a set of Computer-Aided-Design(CAD) tools to aid design of circuits in the presence of transistor degradation mechanisms. These CAD tools not only provide information on the circuit behavior due to degradation but also provide information on the degradation suffered by the individual components in the design and also provide design guidelines in the form of changes to the component parameters to bring down the degradation to specified values. These tools facilitate the designer during circuit design in the presence of degradation mechanisms like Hot Carrier Injection(HCI) and Negative Bias Temperature Insta-bility(NBTI).

Citation:

Ananth Somayaji Goda, Gautam Kapila, "Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms," isqed, pp.416-420, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005

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