Sixth International Symposium on Quality of Electronic Design (ISQED'05) Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP) San Jose, California March 21-March 23 ISBN: 0-7695-2301-3
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.38
This paper presents a cost-effective area-IO DRAM (aDRAM)/Logic integration implemented with CLC (Chip-Laminate-Chip)-based System-in-a-Package (SiP) technology. By inserting 512 area-IOs into the aDRAM, the bandwidth of the area-IO DRAM can achieve 10GB/s when working under 166MHz. An interface module with configurable IO width was also developed to make this implementation platform adoptable by various applications. A performance analysis, including bandwidth and power is also presented in this paper. It is demonstrated that area-IO DRAM/Logic integration with SiP technology provides a significant cost-effective implementation methodology compared with embedded DRAM and off-chip DRAM.
Citation:
Anru Wang, Wayne Dai, "Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP)," isqed, pp.562-566, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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