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Sixth International Symposium on Quality of Electronic Design (ISQED'05)
Controlled-Load Limited Switch Dynamic Logic Circuit
San Jose, California
March 21-March 23
ISBN: 0-7695-2301-3
Jayakumaran Sivagnaname, The University of Michigan, Ann Arbor, MI
Hung C. Ngo, IBM Austin Research Laboratory, Austin, TX
Kevin J. Nowka, IBM Austin Research Laboratory, Austin, TX
Robert K. Montoye, IBM Austin Research Laboratory, Austin, TX
Richard B. Brown, The University of Michigan, Ann Arbor, MI
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounces. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated.
Citation:
Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown, "Controlled-Load Limited Switch Dynamic Logic Circuit," isqed, pp.83-87, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005
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