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Sixth International Symposium on Quality of Electronic Design (ISQED'05)

Controlled-Load Limited Switch Dynamic Logic Circuit

San Jose, California

March 21-March 23

ISBN: 0-7695-2301-3

	ASCII Text	x
	Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown, "Controlled-Load Limited Switch Dynamic Logic Circuit," Quality Electronic Design, International Symposium on, pp. 83-87, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005.

	BibTex	x
	@article{ 10.1109/ISQED.2005.35, author = {Jayakumaran Sivagnaname and Hung C. Ngo and Kevin J. Nowka and Robert K. Montoye and Richard B. Brown}, title = {Controlled-Load Limited Switch Dynamic Logic Circuit}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2301-3}, pages = {83-87}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.35}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Controlled-Load Limited Switch Dynamic Logic Circuit SN - 0-7695-2301-3 SP83 EP87 A1 - Jayakumaran Sivagnaname, A1 - Hung C. Ngo, A1 - Kevin J. Nowka, A1 - Robert K. Montoye, A1 - Richard B. Brown, PY - 2005 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Jayakumaran Sivagnaname, The University of Michigan, Ann Arbor, MI

Hung C. Ngo, IBM Austin Research Laboratory, Austin, TX

Kevin J. Nowka, IBM Austin Research Laboratory, Austin, TX

Robert K. Montoye, IBM Austin Research Laboratory, Austin, TX

Richard B. Brown, The University of Michigan, Ann Arbor, MI

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.35

Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounces. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated.

Citation:

Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown, "Controlled-Load Limited Switch Dynamic Logic Circuit," isqed, pp.83-87, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005

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