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Sixth International Symposium on Quality of Electronic Design (ISQED'05)
Buffer Planning Algorithm Based on Partial Clustered Floorplanning
San Jose, California
March 21-March 23
ISBN: 0-7695-2301-3
Yuchun Ma, Tsinghua University, Beijing, China
Xianlong Hong, Tsinghua University, Beijing, China
Sheqin Dong, Tsinghua University, Beijing, China
Song Chen, Tsinghua University, Beijing, China
Chung-Kuan Cheng, University of California, San Diego
In this paper, we propose a partial clustered floorplanning methodology with buffer planning. The theoretic analyses show that the timing constraints can be transferred into bounding box constraint and the spacing between buffers is somewhat stable. Therefore the critical nets can be controlled by clustering strategy. The cluster strategies in our approach are designed not only for localizing the critical nets, but also for facilitating the buffer insertion of long wires. Based on CBL representation, we devise sub CBL to represent the cluster and embed the optimization of the clusters into the annealing process. In most of previous clustering-based methods, the shape of the cluster was restricted to be a square. In this paper, however, we remove this restriction by treating the cluster as the sub packing. Our method can achieve a very stable performance. Experimental results on MCNC benchmark show the effectiveness of the method and prove correctness of the theoretic analyses.
Citation:
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, "Buffer Planning Algorithm Based on Partial Clustered Floorplanning," isqed, pp.213-219, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005
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