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Sixth International Symposium on Quality of Electronic Design (ISQED'05)
Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment
San Jose, California
March 21-March 23
ISBN: 0-7695-2301-3
ASCII Text
x 
 
O. Semenov, H. Sarbishaei, M. Sachdev, "Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment," Quality Electronic Design, International Symposium on, pp. 427-432, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005.
 
 
BibTex
x
 
@article{ 10.1109/ISQED.2005.17,
author = {O. Semenov and H. Sarbishaei and M. Sachdev},
title = {Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2005},
isbn = {0-7695-2301-3},
pages = {427-432},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.17},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment
SN - 0-7695-2301-3
SP427
EP432
A1 - O. Semenov,
A1 - H. Sarbishaei,
A1 - M. Sachdev,
PY - 2005
KW - Electrostatic discharge (ESD)
KW - electrical overstress (EOS)
KW - LVTSCR
KW - burn-in
KW - latch-up
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
O. Semenov, University of Waterloo, Canada
H. Sarbishaei, University of Waterloo, Canada
M. Sachdev, University of Waterloo, Canada
As technology feature size is reduced, ESD becomes one of the dominant failure modes due to the lower gate oxide breakdown voltage. Also, the holding voltage of LVTSCR devices is reduced with operating temperature increase. As a result, during stress testing (burn-in), the risk of latch-up in LVTSCR is extremely high. In this paper, a new latch-up free LVTSCR-based protection circuit is proposed. It can be reliably used in sub-0.18 um CMOS technologies and burn-in environment. The proposed ESD circuit has higher holding voltage by 1.5X than the conventional LVTSCR structure at burn-in temperature. Under 3kV HBM ESD stress, the developed LVTSCR-based protection circuit has the voltage peak less than the conventional LVTSCR structure and GG-MOSFET by 2X and 1.25X, respectively.
Index Terms:
Electrostatic discharge (ESD), electrical overstress (EOS), LVTSCR, burn-in, latch-up
Citation:
O. Semenov, H. Sarbishaei, M. Sachdev, "Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment," isqed, pp.427-432, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005
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