As the scale and complexity of VLSI circuits increase, Electronic Design Automation (EDA) tools become much more sophisticated and are held to increasing standards of quality. New-generation EDA tools must work correctly on a wider range of inputs, have more internal states, take more effort to develop, and offer fertile ground for programming mistakes. Ensuring quality of a commercial tool in realistic design flows requires rigorous simulation, non-trivial computational resources, accurate reporting of results and insightful analysis. However, time-to-market pressures encourage EDA engineers and chip designers to look elsewhere. Thus, the recent availability of cheap Linux clusters and grids shifts the bottleneck from hardware to logistical tasks, i.e., the speedy collection, reporting and analysis of empirical results. To be practically feasible, such tasks must be automated; they leverage high-performance computing to improve EDA tools. In this work we outline a possible infrastructure solution, called bX, explore relevant use models and describe our computational experience. In a specific application, we use bX to automatically build Pareto curves required for accurate performance analysis of randomized algorithms.