Sixth International Symposium on Quality of Electronic Design (ISQED'05) A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks San Jose, California March 21-March 23 ISBN: 0-7695-2301-3
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.12
We propose an adaptive scalable architecture suitable for performing real-time algorithm-specific tasks. The architecture is based on Globally Asynchronous and Locally Synchronous (GALS) design paradigm. We demonstrate that for different real-time commercial applications with algorithm-specific jobs like online transaction processing, Fourier transform etc., the proposed architecture allows dynamic load-balancing and adaptive inter-task voltage scaling. The architecture can also detect process-shifts for the individual processing units and determine their appropriate operating conditions. Simulation results for two representative applications show that for a random job distribution, we obtain up to 67% improvement in MOPS/W (millions of operations per second per watt) over a fully synchronous implementation.
Citation:
Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy, "A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks," isqed, pp.358-363, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||