This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Conventional STA tools represent an electrical waveform at the intermediate node of a logic circuit by its arrival time and slope. In general these two parameters are calculated based on the time instances at which the input waveform passes through predetermined voltage levels. However, to properly account for the impact of noise on the shape of a waveform, it is insufficient to model the waveform by using only two parameters. The key contribution of the proposed methodology is to base the timing analysis on the sensitivity of the output to input waveforms and accurately, yet efficiently, propagate equivalent electrical waveforms throughout a VLSI circuit. A hybrid technique combines the sensitivity-based approach with an energy-based technique to increase the efficiency of gate delay propagation. Experimental results demonstrate higher accuracy of our methodology compared to the best of the existing techniques. The sensitivity-based technique is compatible with the current level of gate characterization in conventional ASIC cell libraries, and so it can be easily incorporated into the commercial STA tools to enhance their accuracy.