This paper presents a novel process-tolerant multi-level signaling system for on-chip interconnects. Novel multi-level driver and receiver designs are presented which are robust in the presence of process-induced parameter variation and uncertainties. Monte Carlo analyses show that the interconnect delay and total average power are normally distributed with a standard deviation of around 9.46% and 15.96% respectively for a 10mm line in 100nm technology. Individual parameter sensitivity analyses show that the total average power is most influenced by supply voltage and effective gate length, and delay is most influenced by interconnect resistance and capacitance. Yield of high performance and low power bins in 100nm technology under process variations using the proposed multi-level signaling system is 36.1%, yield of high performance bins is 27.3% and yield of low power bins is 25.1% and yield of bad bins is only 11.5%.