Reduced Test Application Time Based on Reachability Analysis

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Sixth International Symposium on Quality of Electronic Design (ISQED'05)

San Jose, California

March 21-March 23

ISBN: 0-7695-2301-3

	ASCII Text	x
	Th. Haniotakis, S. Tragoudas, G. Pani, "Reduced Test Application Time Based on Reachability Analysis," Quality Electronic Design, International Symposium on, pp. 232-237, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005.

	BibTex	x
	@article{ 10.1109/ISQED.2005.102, author = {Th. Haniotakis and S. Tragoudas and G. Pani}, title = {Reduced Test Application Time Based on Reachability Analysis}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2301-3}, pages = {232-237}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.102}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Reduced Test Application Time Based on Reachability Analysis SN - 0-7695-2301-3 SP232 EP237 A1 - Th. Haniotakis, A1 - S. Tragoudas, A1 - G. Pani, PY - 2005 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Th. Haniotakis, Southern Illinois University Carbondale

S. Tragoudas, Southern Illinois University Carbondale

G. Pani, Southern Illinois University Carbondale

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.102

A test application method to reduce the test application time in full scan designs is presented. It can be used either during or after the test pattern generation phase so that one or more patterns can be reached from an already scanned pattern using scan reapply or scan shift operations. The presented approach is based on established methods for reachability analysis in sequential verification and a fault grading algorithm to ensure that all targeted faults are covered.

Citation:

Th. Haniotakis, S. Tragoudas, G. Pani, "Reduced Test Application Time Based on Reachability Analysis," isqed, pp.232-237, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005

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