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5th International Symposium on Quality Electronic Design (ISQED'04)
Layout Printability Optimization Using a Silicon Simulation Methodology
San Jose, California
March 22-March 24
ISBN: 0-7695-2093-6
ASCII Text
x 
 
Michel Cote, Philippe Hurat, "Layout Printability Optimization Using a Silicon Simulation Methodology," Quality Electronic Design, International Symposium on, pp. 159-164, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004.
 
 
BibTex
x
 
@article{ 10.1109/ISQED.2004.1283667,
author = {Michel Cote and Philippe Hurat},
title = {Layout Printability Optimization Using a Silicon Simulation Methodology},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2004},
issn = {2003116307},
pages = {159-164},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283667},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Layout Printability Optimization Using a Silicon Simulation Methodology
SN - 2003116307
SP159
EP164
A1 - Michel Cote,
A1 - Philippe Hurat,
PY - 2004
KW - null
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Michel Cote, Synopsys, Inc.
Philippe Hurat, Synopsys, Inc.

The manufacturing complexity at the 90nm and 65nm technology nodes severally impacts the design. The traditional use of design rule based verification is no longer a guarantee of high yield once the chip has been manufactured. This paper describes many of the trends behind this phenomenon.

A new approach to layout that moves from an abstraction approach to a modeling approach is proposed. In this new methodology layouts are processed using resolution enhancement techniques and the results are simulated using lithographical models for a specific manufacturing process. The simulation results are used to identify critical regions in the layouts. The layouts are then optimized based on this analysis to improve their printability, manufacturability and yield.

Citation:
Michel Cote, Philippe Hurat, "Layout Printability Optimization Using a Silicon Simulation Methodology," isqed, pp.159-164, 5th International Symposium on Quality Electronic Design (ISQED'04), 2004
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