In this paper we propose a new design methodology targeted for core-based designs using parameterized macro-cells (PMC?s). This methodology provides the flexibility for instance-based cores to be easily customized for application requirements. By using few scaling parameters to characterize a PMC, a macrocell can be instantiated in virtually any size depending on the required performance. Moreover, a new first-order macro delay model is proposed which is a function of the scaling parameters of the PMC which enables accurate delay predictions at the subsystem/core level. The proposed delay model is suitable for use by a delay optimizer to determine the optimum scaling parameters of individual PMC?s in a core. A PMC library has been developed and used to design cores for communications applications. To demonstrate the effectiveness of the proposed methodology, several subsystems used in a channel LDPC decoder were synthesized using this library where the individual PMC?s were optimized for minimum delay. The resulting custom-quality layout have areas ranging from 40 \times 100?m² to 380 \times 200?m² and delay in the range of 1:6ns to 10ns in 0:18?m, 1:8V CMOS technology.