We present a methodology for on-chip characterization of the pin-to-pin propagation delay of single standard cells. A periodic waveform is provided to an input pin of the standard cell under characterization, while keeping all other inputs at non-controlling logic values. Simultaneous random sampling is then applied to input and output periodic waveforms, and propagation delay measures are obtained from the joint signal probabilities of the samples.The proposed technique is suitable for on-chip implementation because it is simple and it doesn't require timing-accurate control signals. On the other hand, on-chip measurements can be applied to a large number of cells working in different operating conditions, providing valuable information for characterizing and validating timing models.A test chip has been realized in a 0.18?m embedded NVM CMOS technology, and used to monitor the sub-nanosecond timing behavior of a standard cell library during process development.