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Fourth International Symposium on Quality Electronic Design
Reliability Evaluation for Integrated Circuit with Defective Interconnect under Electromigration
San Jose, California
March 24-March 26
ISBN: 0-7695-1881-8
Xiangdong Xuan, Georgia Institute of Technology
Adit D. Singh, Auburn University
Abhijit Chatterjee, Georgia Institute of Technology
In electromigration degradation process the existing physical defects on interconnect play a critical role by significantly accelerating the EM damage under increased current density and elevated temperature. In this work the simulation models were upgraded in the IC reliability simulator ARET to incorporate the effect of interconnect physical defects in expected lifetime prediction. Then based on the statistical approach, a probability model was developed to evaluate the system-level circuit reliability with defective interconnect under EM degradation. The probability model has been successfully implemented in ARET tool to simulate and evaluate both interconnect and circuit level reliabilities.
Citation:
Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee, "Reliability Evaluation for Integrated Circuit with Defective Interconnect under Electromigration," isqed, pp.29, Fourth International Symposium on Quality Electronic Design, 2003
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