The data paths of most contemporary general and special purpose processors include registers, adders and other arithmetic circuits. If these circuits are also used for Built-In Self-Test, the extra area required for embedding testing structures can be cut down efficiently. Several schemes based on accumulators, subtracters, multipliers and shift registers have been proposed and analyzed in the past for parallel test response compaction, whereas some efforts have also been devoted in the bit-serial response compaction case. In this paper, we analyze and evaluate the bit-serial version of a recently proposed scheme for parallel test response compaction [5]. Experimental results on the ISCAS'85 benchmark circuits indicate that the post-compaction fault coverage drop attained by the new scheme is significantly lower than other already known accumulator-based compaction schemes.