ESD: Design For IC Chip Quality and Reliability

I
ISQED
2000
First International Symposium on Quality of Electronic Design
Abstract - ESD: Design For IC Chip Quality and Reliability

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Charvaka Duvvury

First International Symposium on Quality of Electronic Design

San Jose, California

March 20-March 22

ISBN: 0-7695-0525-2

	ASCII Text	x
	Charvaka Duvvury, "ESD: Design For IC Chip Quality and Reliability," Quality Electronic Design, International Symposium on, pp. 251, First International Symposium on Quality of Electronic Design, 2000.

	BibTex	x
	@article{ 10.1109/ISQED.2000.838880, author = {Charvaka Duvvury}, title = {ESD: Design For IC Chip Quality and Reliability}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2000}, isbn = {0-7695-0525-2}, pages = {251}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2000.838880}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - ESD: Design For IC Chip Quality and Reliability SN - 0-7695-0525-2 SP EP A1 - Charvaka Duvvury, PY - 2000 KW - Electrostatic Discharge KW - ESD design KW - Human Body Model KW - Machine Model KW - Charged Device Model KW - ESD simulations VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Charvaka Duvvury, Texas Instruments

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2000.838880

ESD is a major concern for IC chip quality both as as building-in-reliability requirement and as a need for long-term field operation requirement. The damage phenomena, either from human handling or machine contact, could appear as thermal damage and oxide rupture. In this paper, the IC damage phenomena due to ESD, the effects on the IC functionality, the proper methods to overcome these with on-chip protection designs, and the challenges facing these protection methods with the advanced process and package technologies will be presented. Simulation and modeling methods that are currently used to improve the protection designs will also be reviewed.

Index Terms:

Electrostatic Discharge, ESD design, Human Body Model, Machine Model, Charged Device Model, ESD simulations

Citation:

Charvaka Duvvury, "ESD: Design For IC Chip Quality and Reliability," isqed, pp.251, First International Symposium on Quality of Electronic Design, 2000

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.