EMI (electromagnetic interference) noise has become more significant problems in high-speed electronic systems. To analyze the EMI problems, LSIs should be determined carefully as the source of EMI noise. However as the circuit size of the LSIs becomes larger, it becomes more difficult to analyze the noise of these circuits by using a transistor-level simulator. Thus designers need a simulator that covers full-chip size for noise analysis.In this paper, we propose a new EMI noise simulation methodology that uses a gate-level representation for the first time. The noise from the logic gates is simply modeled by a FFT process based on the superimposed triangular current waveform. Because of the compactness of the model, we can reduce the computation dramatically and accomplish a large simulation.Furthermore, we developed a prototype of simulator 'LEMINGS' to demonstrate the proposed method for conventional ASIC design flows. The experimental results show that our new EMI analysis method has achieved an outstanding performance, a high capacity to simulate the whole design and a high accuracy that is equivalent to the transistor-level simulator. Information obtained from LEMINGS can also help designers to improve the LSI and electronic systems' design quality.