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First International Symposium on Quality of Electronic Design
GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design
San Jose, California
March 20-March 22
ISBN: 0-7695-0525-2
ASCII Text
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Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike Hirokazu Yonezawa, Yoshiyuki Kawakami, "GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design," Quality Electronic Design, International Symposium on, pp. 73, First International Symposium on Quality of Electronic Design, 2000.
 
 
BibTex
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@article{ 10.1109/ISQED.2000.838857,
author = {Lifeng Wu and Jingkun Fang and Heting Yan and Ping Chen and Alvin I-Hsien Chen and Yoshifumi Okamoto and Chune-Sin Yeh and Zhihong Liu and Nobufusa Iwanishi and Norio Koike Hirokazu Yonezawa and Yoshiyuki Kawakami},
title = {GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2000},
isbn = {0-7695-0525-2},
pages = {73},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2000.838857},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design
SN - 0-7695-0525-2
SP
EP
A1 - Lifeng Wu,
A1 - Jingkun Fang,
A1 - Heting Yan,
A1 - Ping Chen,
A1 - Alvin I-Hsien Chen,
A1 - Yoshifumi Okamoto,
A1 - Chune-Sin Yeh,
A1 - Zhihong Liu,
A1 - Nobufusa Iwanishi,
A1 - Norio Koike Hirokazu Yonezawa,
A1 - Yoshiyuki Kawakami,
PY - 2000
KW - Hot Carrier Effect
KW - Gate level modeling
KW - Gate level simulation
KW - Circuit reliability simulation
KW - VLSI
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Lifeng Wu, BTA Technology Inc.
Jingkun Fang, BTA Technology Inc.
Heting Yan, BTA Technology Inc.
Ping Chen, BTA Technology Inc.
Alvin I-Hsien Chen, BTA Technology Inc.
Yoshifumi Okamoto, BTA Technology Inc.
Chune-Sin Yeh, BTA Technology Inc.
Zhihong Liu, BTA Technology Inc.
Nobufusa Iwanishi, Matsushita Electronics Co.
Norio Koike Hirokazu Yonezawa, Matsushita Electronics Co.
Yoshiyuki Kawakami, Matsushita Electronics Co.
Gate level circuit simulation on hot carrier degradation is introduced for the first time by the GLACIER system presented in this paper. The inherent advantages such as high speed and high capacity of the gate level simulation as compared to the traditional transistor level hot carrier simulation makes the design-in reliability simulation possible and practical for the deep submicron VLSI circuit designs with millions of transistors. By virtue of a unique ratio based modeling technique, GLACIER system provides a very high accuracy, which is mostly within 1% difference of transistor level hot carrier simulation.
Index Terms:
Hot Carrier Effect, Gate level modeling, Gate level simulation, Circuit reliability simulation, VLSI
Citation:
Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike Hirokazu Yonezawa, Yoshiyuki Kawakami, "GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design," isqed, pp.73, First International Symposium on Quality of Electronic Design, 2000
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