The paper presents an analysis of the suitability of the architecture of dynamic SMP clusters with communication on the fly for massively parallel fine grain numerical computations. It is assumed that the proposed architecture is implemented using the highly modular " system on chip" and "network on chip" technology. This technology is considered to provide soon a very large number of co-operating processors embedded in a single parallel system, thus enabling massively parallel computations. The proposed architecture of dynamic clusters with communication on the fly meets requirements of large scale fine grain computations and can be successfully applied in this technology. Experimental simulation results are presented concerning efficiency of fine grain parallel implementation of a typical numerical problem which is matrix multiplication based on recursive data decomposition. Selection of optimal parallel computation grain is discussed. Estimations of the efficiency of the proposed methods for fine grain computations for large problem size are presented.