The paper presents an algorithm for scheduling parallel tasks in a parallel architecture based on multiple dynamic SMP clusters. Processors can be switched between shared memory modules in the runtime. Memory modules and processors are organized in computational System on Chip modules of a fixed size and are inter.connected by a local communication network implemented in a Network. on.Chip technology (NoC). Processors located in the same SoC module can share their data and communicate using a technique of data transfers on the fly. A number of such SoC modules can be connected using a global interconnection network to form a larger infrastructure. The presented algorithm schedules initial macro dataflow program graph for such an architecture with a given number of SoC modules, considering a fixed size of a module. First, it distributes program graph nodes among processors, assuming no distribution between SoC modules. Then it transforms and schedules computations and communications to use processor switching and read on the fly facilities. Finally, using genetic algorithm, it divides the whole set of processors into subsets of a given size, which then are mapped to separate SoC modules.