G-H. Asadi, V. Sridharan, M. B. Tahoori, D. R. Kaeli, "Balancing Performance and Reliability in the Memory Hierarchy," Performance Analysis of Systems and Software, IEEE International Symmposium on, pp. 269-279, IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005., 2005.

@article{ 10.1109/ISPASS.2005.1430581,
author = {G-H. Asadi and V. Sridharan and M. B. Tahoori and D. R. Kaeli},
title = {Balancing Performance and Reliability in the Memory Hierarchy},
journal ={Performance Analysis of Systems and Software, IEEE International Symmposium on},
volume = {0},
year = {2005},
isbn = {0-7803-8965-4},
pages = {269-279},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISPASS.2005.1430581},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - Performance Analysis of Systems and Software, IEEE International Symmposium on
TI - Balancing Performance and Reliability in the Memory Hierarchy
SN - 0-7803-8965-4
SP269
EP279
A1 - G-H. Asadi,
A1 - V. Sridharan,
A1 - M. B. Tahoori,
A1 - D. R. Kaeli,
PY - 2005
KW - null
VL - 0
JA - Performance Analysis of Systems and Software, IEEE International Symmposium on
ER -