8th International Symposium on Parallel Architectures,Algorithms and Networks (ISPAN'05) Scalable Multistage Network for Multiprocessor System-on-Chip Design Las Vegas, Nevada, USA December 07-December 09 ISBN: 0-7695-2509-1
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISPAN.2005.77
This paper presents a micro-network that is a generic, scalable and multi-stage interconnect architecture for systems on a chip (SoC). The network architecture relies on a packet switching and point-to-point bi-directional links between the routers implementing the micro network. The NoC provides a configurable number of OCP compliant communication interfaces for both initiators (master) and targets (slave). This network has been used in a multiprocessor SoC with 16 initiators 16 slaves, and compared with an AMBA bus in terms of latency and saturation threshold.
Citation:
Sammy Meftali, Jean-luc Dekeyser, Isaac D. Scherson, "Scalable Multistage Network for Multiprocessor System-on-Chip Design," ispan, pp.352-357, 8th International Symposium on Parallel Architectures,Algorithms and Networks (ISPAN'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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