2000 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '00) A Parallel Processor Architecture for Prefetching Dallas/Richardson, Texas, USA December 07-December 07 ISBN: 0-7695-0936-3
Prefetching brings data into the cache before it is expected by the processor, thereby eliminating a potential cache miss. There are two major prefetching schemes. In a software scheme, the compiler predicts the memory access pattern and places prefetch instructions into the code. In a hardware scheme the hardware predicts the memory access pattern and brings data into the cache before required by the processor. This paper proposes a hardware prefetching scheme, where a second processor is used for prefetching data for the primary processor. The scheme does not predict memory access patterns, but rather uses the second processor to run ahead of the primary processor so as to detect future memory accesses and prefetch these references.
Citation:
S. Kim, S. Manoharan, "A Parallel Processor Architecture for Prefetching," ispan, pp.254, 2000 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '00), 2000 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||